Timings random access memory: What are they, and how do they affect Windows performance?

Users who are trying to improve the performance of their computer with their own hands are well aware that the principle “the more the better” does not always work for computer components. For some of them, additional characteristics are introduced that affect the quality of the system no less than volume. And for many devices this concept speed. Moreover, this parameter affects the performance of almost all devices. There are also few options here: the faster it turns out, the better. But let's be clear about exactly how the concept of speed characteristics in RAM affects the performance of Windows.

The speed of the RAM module is the main indicator of data transfer. The larger the declared number, the faster the computer will “throw the data itself into the furnace” of RAM and “remove” them from there. In this case, the difference in the amount of memory itself can be reduced to nothing.

Speed ​​vs volume: which is better?

Imagine a situation with two trains: the first is huge but slow, with old gantry cranes slowly loading and unloading cargo. And the second: compact, but fast with modern fast cranes, which, thanks to their speed, do the work of loading and delivering many times faster. The first company advertises its volumes without saying that the cargo will have to wait a very long time. And the second one, with smaller volumes, however, will have time to process loads many times more. Much, of course, depends on the quality of the road itself, and the promptness of the driver. But, as you understand, the combination of all factors determines the quality of cargo delivery. Is the situation similar with the RAM sticks in the motherboard slots?

Bearing in mind the above example, when we are faced with a nomenclature choice. When choosing a bar somewhere in the online store, we look for the abbreviation DDR, but it is likely that we may also come across the good old PC2, PC3 and PC4 standards that are still in use. So, often beyond generally accepted standards such as DDR3 1600 RAM you can see the description PC3 12800, Near DDR4 2400 RAM often worth PC4 19200 etc. This is the data that will help explain how quickly our cargo will be delivered.

We read the characteristics of memory: now you will understand everything yourself

Users who know how to operate with numbers in the octal system link such concepts quickly. Yes, here we are talking about those very expressions in bits / bytes:

1 byte = 8 bits

Keeping this simple equation in mind, we can easily calculate that DDR 3 1600 means PC speed 3 12800 bps Similar to this DDR 4 2400 means PC4 with speed 19200 bps But if everything is clear with the transfer rate, then what are timings? And why two seemingly identical modules due to the difference in timings can show in special programs different performance levels?

Timing characteristics should be presented, among others, for RAM sticks by quad numbers through a dash ( 8-8-8-24 , 9-9-9-24 etc). These numbers indicate the specific amount of time it takes for the RAM module to access data bits through the memory array tables. To simplify the concept in the previous sentence, the term “delay” was introduced:

Delay is a concept that characterizes how quickly the module gets access to “itself” (may the techies forgive me for such a free interpretation). That is, how fast the bytes move inside the chips of the bar. And here the opposite principle applies: the smaller the number, the better. Lower latency means faster access, which means data will reach the processor faster. Timings “measure” the delay time ( waiting period – CL) memory chip while it is processing some process. And the number in the composition of several hyphens means how much time cycles this memory module will “slow down” the information or data that the processor is currently waiting for.

And what does this mean for my computer?

Imagine, after a long time ago you made a purchase of a laptop, you decided to go with an existing one. Among other things, guided by the pasted label or on the basis of benchmark programs, it can be established that, according to the characteristics of the timings, the module falls into the category CL-9(9-9-9-24) :

That is, this module will deliver information to the CPU with a delay 9 conditional loops: not the fastest, but not the worst option either. As such, there's no point in getting hung up on getting a bar with lower latency (and, in theory, higher performance specs). For example, as you may have guessed, 4-4-4-8 , 5-5-5-15 and 7-7-7-21, whose number of cycles is respectively 4, 5 and 7 .

the first module is ahead of the second by almost a third of the cycle

As you know from the article " “, the timing parameters include one more important value:

• CL – CAS Latency module received command – the module started responding“. It is this conditional period that is spent on the response to the processor from the module / modules
• tRCD- delay RAS to CAS- the time spent on the activation of the line ( RAS) and column ( CAS) - this is where the data in the matrix is ​​\u200b\u200bstored (each memory module is organized according to the type of matrix)
• tRP– filling (Charging) RAS- the time spent on terminating access to one line of data and starting access to the next
• tRAS- means how long the memory itself will have to wait for the next access to itself
• cmd– command rate– time spent on the cycle “ chip activated – first command received(or the chip is ready to receive a command)”. Sometimes this parameter is omitted: it is always one or two cycles ( 1T or 2T).

The “participation” of some of these parameters in the principle of calculating the speed of the RAM can also be expressed in the following figures:

In addition, the delay time until the bar starts sending data can be calculated by yourself. Here's a simple formula at work:

Delay time(sec) = 1 / transmission frequency(Hz)

Thus, from the figure with CPUD, we can calculate that a DDR 3 module operating at a frequency of 665-666 MHz (half of the value declared by the manufacturer, i.e. 1333 MHz) will produce approximately:

1 / 666 000 000 = 1,5 ns (nanoseconds)

full cycle period (takt time). And now we consider the delay for both options presented in the figures. With timings CL- 9 the module will issue “brakes” with a period 1,5 X 9 = 13,5 ns, at CL- 7 : 1,5 X 7 = 10,5 ns

What can be added to the drawings? From them it is clear that below RAS charge cycle, topics will work faster and myself module. Thus, the total time from the moment the command was given to “charge” the module cells and the actual receipt of data by the memory module is calculated by a simple formula (all these indicators of a CPU-Z utility should be issued):

tRP + tRCD + CL

As can be seen from the formula, the lower each from indicated parameters, topics will be faster your RAM work.

How can you influence them or adjust the timings?

The user, as a rule, does not have very many opportunities for this. If there is no special setting for this in the BIOS, the system will configure the timings automatically. If there are any, you can try to set the timings manually from the suggested values. And having exposed, follow the stability. I admit, I am not a master of overclocking and have never plunged into such experiments.

Timings and system performance: choose by volume

If you do not have a group of industrial servers or a bunch of virtual servers, the timings will have absolutely no effect. When we use this concept, we are talking about units nanosecond. So at stable operation of the OS memory delays and their impact on performance, solid, it would seem, in relative terms, in absolute terms insignificant: a person simply cannot physically notice changes in speed. Benchmark programs will certainly notice this, however, if one day you are faced with the choice of whether to purchase 8 GB DDR4 at speed 3200 or 16 GB DDR4 with speed 2400 don't hesitate to choose second option. The choice in favor of volume, rather than speed, is always clearly marked for a user with a custom OS. And after taking a couple of overclocking lessons on how to work and setting the timings for RAM, you can then achieve an improvement in performance.

So what do you care about timings?

Almost yes. However, there are a few points here that you probably already managed to grab yourself. In an assembly that uses multiple processors and a discrete graphics card with its own memory chip, timings RAM Dont Have no values. The situation with integrated (built-in) video cards is changing a little, and some very advanced users feel lag in games (as far as these video cards even allow you to play). This is understandable: when all the computing power falls on the processor and a small (most likely) amount of RAM, any load affects. But, again, based on other people's research, I can convey their results to you. On average, the performance loss in speed by eminent benchmarks in various tests with a decrease or increase in timings in assemblies with integrated or discrete cards fluctuates around 5% . Consider this a fixed number. Whether it's a lot or a little, you be the judge.

Read: 2 929

CAS Latency (Column Address Strobe Latency) or CL- CAS latency indicator. By it is meant the waiting time between the request of the processor and the moment the first data cell from memory becomes available. At the same time, the desired line should already be active, if it is not, additional time will be required. Time is calculated in cycles.

CAS latency in memory modules:

• SDR SDRAM - 1, 2, 3 cycles;
• DDR SDRAM - 2, 2.5 cycles.

The CAS latency designation on memory modules is produced as "CAS" or "CL". And the indicator CAS2, CAS-2, CAS=2, CL2, CL-2 or CL=2 indicates the duration of the delay (in this case equal to 2 cycles).

The lower the CAS Latency, the better.

In asynchronous DRAM, the interval is specified in nanoseconds. Synchronous DRAMs display the interval in clocks (cycles).

Dynamic RAM is arranged in a rectangular array. Each row is selected by a horizontal row. Sending a logic high signal on a given row allows the MOSFET to be represented on that row by connecting each storage capacitor to the corresponding vertical bit strip. Each bit line is connected to an amplifier which produces a small voltage change. This amplifier signal subsequently exits the DRAM chip to update the string.

When there is no activity on a line, the array is idle and only part of the lines is in the ready state. At the same time, the voltage level is medium. It deviates towards greater or lesser, depending on the activity of the line.

To access memory, strings must first be selected and loaded into the amplifier. Only after that the row becomes active, and the columns are available for read and write operations.

Let's take a typical 1 GB SDRAM memory module as an example. It can contain up to 8 separate gigabit DRAM chips, each of which can hold up to 128 MB of memory. Inside, each chip is further divided into 8 banks of 227 Mb each, each containing a separate DRAM array. Each array contains 214 = 16384 rows of 213 = 8192 bits each. One byte of memory (from each chip; 64 bits in total from the entire DIMM) is capable of handling a 3-bit bank number, a 14-bit row address, and a 10-bit column address.

Memory Timing Examples

Only CAS latency

Generation		Transfer rate	beat time	Frequency	Cycle		First word	fourth word	eighth word

When overclocking a computer, we pay more attention to such components as a processor and a video card, and memory, as an equally important component, is sometimes bypassed. But it is precisely the fine tuning of the memory subsystem that can additionally increase the speed of rendering a scene in three-dimensional editors, reduce the time for compressing a home video archive, or add a couple of frames per second in your favorite game. But even if you're not overclocking, the extra performance never hurts, especially since the risk is minimal with the right approach.

Gone are the days when access to the memory subsystem settings in BIOS Setup was closed from prying eyes. Now there are so many of them that even a trained user can get confused with such a variety, not to mention a simple "user". We will try to explain as much as possible the steps necessary to improve system performance through the simplest settings of the main timings and, if necessary, some other parameters. AT this material we will look at an Intel platform with DDR2 memory based on a chipset from the same company, and the main goal will be to show not how much the performance will increase, but how exactly it needs to be increased. Concerning alternative solutions, then for DDR2 memory our recommendations are almost completely applicable, and for conventional DDR (lower frequency and delays, and higher voltage) there are some reservations, but in general, the tuning principles are the same.

As you know, the lower the delay, the lower the memory latency and, accordingly, the higher the speed. But you should not immediately and thoughtlessly reduce the memory settings in the BIOS, as this can lead to completely opposite results, and you will either have to return all the settings to their place, or use Clear CMOS. Everything must be carried out gradually - changing each parameter, restarting the computer and testing the speed and stability of the system, and so on each time, until stable and productive indicators are achieved.

At the moment, the most relevant type of memory is DDR2-800, but it has appeared recently and is only gaining momentum. The next type (or rather, the previous one), DDR2-667, is one of the most common, and DDR2-533 is already starting to disappear from the scene, although it is present on the market in due quantity. It makes no sense to consider DDR2-400 memory, since it has practically disappeared from everyday life. Each type of memory module has a certain set of timings, and for greater compatibility with the variety of equipment available, they are slightly overestimated. So, in the SPD of DDR2-533 modules, manufacturers usually indicate time delays of 4-4-4-12 (CL-RCD-RP-RAS), in DDR2-667 - 5-5-5-15 and in DDR2-800 - 5- 5-5-18, with a standard supply voltage of 1.8-1.85 V. But nothing prevents them from being reduced to increase system performance, and if the voltage is raised to only 2-2.1 V (which for memory will be within norms, but cooling still does not hurt) it is quite possible to set even more aggressive delays.

As a test platform for our experiments, we chose the following configuration:

• Motherboard: ASUS P5B-E (Intel P965, BIOS 1202)
• Processor: Intel Core 2 Extreme X6800 (2.93 GHz, 4 MB cache, FSB1066, LGA775)
• Cooling System: Thermaltake Big Typhoon
• Video card: ASUS EN7800GT Dual (2xGeForce 7800GT, but only "half" of the video card was used)
• HDD: Samsung HD120IJ (120 GB, 7200 rpm, SATAII)
• Drive: Samsung TS-H552 (DVD+/-RW)
• Power supply: Zalman ZM600-HP

Two 1 GB DDR2-800 modules from Hynix (1GB 2Rx8 PC2-6400U-555-12) were used as RAM, which made it possible to expand the number of tests with different modes memory work and timing combinations.

Here is a list of the necessary software that allows you to check the stability of the system and fix the results of memory settings. For check stable operation memory, you can use such test programs as Testmem, Testmem+, S&M, Prime95, as a utility for setting timings "on the fly" in the Windows environment, it is used MemSet (for Intel and AMD platforms) and A64Info (for AMD only). Finding out the justification of experiments on memory can be done by the archiver WinRAR 3.70b(there is a built-in benchmark), the program SuperPI, which calculates the value of the number Pi, with a test package Everest(there is also a built-in benchmark), SiSoft Sandra etc.

The main settings are made in BIOS Setup. To do this, during system startup, press the key Del, F2 or another, depending on the manufacturer of the board. Next, we are looking for a menu item responsible for memory settings: timings and operating mode. In our case, the desired settings were in Advanced/Chipset Setting/North Bridge Configuration(timings) and Advanced/Configure System Frequency(mode of operation or, more simply, memory frequency). In the BIOS of other boards, the memory settings may be in "Advanced Chipset Features" (Biostar), "Advanced/Memory Configuration" (Intel), "Soft Menu + Advanced Chipset Features" (abit), "Advanced Chipset Features/DRAM Configuration" (EPoX), "OverClocking Features/DRAM Configuration" (Sapphire), "MB Intelligent Tweaker" (Gigabyte, to activate the settings, you need to click in the main BIOS window Ctrl+F1) etc. The supply voltage is usually changed in the menu item responsible for overclocking and is designated as "Memory Voltage", "DDR2 OverVoltage Control", "DIMM Voltage", "DRAM Voltage", "VDIMM", etc. Also, for different boards from the same manufacturer, the settings may differ both in name and placement, and in number, so in each case you will have to refer to the instructions.

If there is no desire to raise the operating frequency of the modules (subject to the possibilities and support from the board) above its nominal value, then we can limit ourselves to reducing the delays. If so, then you will most likely have to resort to increasing the supply voltage, as well as lowering the timings, depending on the memory itself. To change the settings, it is enough to transfer the necessary items from the "Auto" mode to "Manual". We are interested in the main timings, which are usually found together and are called as follows: CAS# Latency Time (CAS, CL, Tcl, tCL), RAS# to CAS# Delay (RCD, Trcd, tRCD), RAS# Precharge (Row Precharge Time, RP, Trp, tRP) and RAS# Activate to Precharge (RAS, Min.RAS# Active Time, Cycle Time, Tras, tRAS). There is also one more parameter - Command Rate (Memory Timing, 1T / 2T Memory Timing, CMD-ADDR Timing Mode) which takes the value 1T or 2T (another value appeared in the AMD RD600 chipset - 3T) and is present on the AMD platform or in NVidia chipsets (in Intel logic it is locked at 2T). When this parameter is reduced to one, the performance of the memory subsystem increases, but its maximum possible frequency decreases. When trying to change the basic timings on some motherboards can expect "pitfalls" - turning off automatic tuning, we thus reset the values ​​of sub-timings (additional timings that affect both the frequency and memory performance, but not as significantly as the main ones), as, for example, on our test board. In this case, you will have to use the MemSet program (preferably latest version) and view the values ​​of sub-timings (sub-timings) for each mode of memory operation in order to set similar ones in the BIOS "e.

If the names of the delays do not match, then the "method of scientific poke" works well here. Slightly changing additional settings in BIOS Setup, we check with the program what, where and how has changed.

Now, for a memory operating at a frequency of 533 MHz, you can try to set 3-3-3-9 or even 3-3-3-8 instead of the standard delays 4-4-4-12 (or some other option). If the system does not start with these settings, we increase the voltage on the memory modules to 1.9-2.1 V. Above is not recommended, even at 2.1 V it is advisable to use additional cooling memory (the simplest option is to direct air flow from a conventional cooler to them). But first, you need to conduct tests with standard settings, for example, in the WinRAR archiver (Tools / Benchmark and hardware test), which is very sensitive to timings. After changing the parameters, we check again and, if the result satisfies, we leave it as it is. If not, as it happened in our testing, then using the MemSet utility in the Windows environment (this operation can either freeze the system or, even worse, make it completely inoperable) or use BIOS Setup to raise RAS # to CAS by one # Delay and test again. After that, you can try to decrease the RAS # Precharge parameter by one, which will slightly increase the performance.

We do the same for DDR2-667 memory: instead of the values ​​5-5-5-15 we set 3-3-3-9. When conducting tests, we also had to increase RAS# to CAS# Delay, otherwise the performance was no different from the standard settings.

For a system using DDR2-800, latencies can be reduced to 4-4-4-12 or even 4-4-3-10, depending on the specific modules. In any case, the selection of timings is purely individual, and it is rather difficult to give specific recommendations, but the examples given may well help you fine-tune the system. And do not forget about the supply voltage.

As a result, we tested with eight different options and combinations of memory modes and its delays, and also included in the tests the results of overclocker memory - Team Xtreem TXDD1024M1066HC4, which worked at an effective frequency of 800 MHz with timings of 3-3-3-8. So, for the 533 MHz mode, three combinations came out with timings 4-4-4-12, 3-4-3-8 and 3-4-2-8, for 667 MHz there are only two - 5-5-5-15 and 3 -4-3-9, and for the 800 MHz mode, as in the first case, three - 5-5-5-18, 4-4-4-12 and 4-4-3-10. The following test packages were used: the memory subtest from the PCMark05 synthetic package, the WinRAR 3.70b archiver, the Pi calculation program SuperPI, and the Doom 3 game (resolution 1024x768, graphics quality High). Memory latency was checked by the built-in Everest benchmark. All tests were run under Windows XP Professional Edition SP2. The presented results in the diagrams are arranged by operating modes.

As you can see from the results, the difference in some tests is insignificant, and sometimes even miserable. This is because system bus A Core 2 Duo processor of 1066 MHz has a theoretical bandwidth of 8.5 Gb/s, which is equivalent to the bandwidth of dual-channel DDR2-533 memory. When using faster memory, the FSB becomes the limiting factor in system performance. Reducing latency leads to an increase in performance, but not as noticeable as increasing the memory frequency. When using the AMD platform as a test bench, one could observe a completely different picture, which we will do next time, if possible, but for now let's return to our tests.

In synthetics, the performance increase with decreasing delays for each of the modes was 0.5% for 533 MHz, 2.3% for 667 MHz and 1% for 800 MHz. A significant increase in performance is noticeable when switching from DDR2-533 to DDR2-667 memory, but changing from 667 to DDR2-800 does not provide such an increase in speed. Also, memory at a lower level and with low timings is very close to a higher-frequency version, but with nominal settings. And this is true for almost every test. For the WinRAR archiver, which is quite sensitive to timing changes, the performance indicator has slightly increased: 3.3% for DDR2-533 and 8.4% for DDR2-667/800. The calculation of the eight-millionth digit of pi treated various combinations in percentage terms better than PCMark05, albeit slightly. The gaming application does not much favor DDR2-677 with 5-5-5-15 timings, and only lowering the latter allowed us to bypass the slower memory (which, as it turned out, doesn't care what timings it costs) by two frames. The DDR2-800 memory setting provided another two frames gain, and the overclocker variant, which had a good gap in the rest of the tests, didn't get much ahead of its less expensive counterpart. Nevertheless, apart from the processor and memory, there is one more link - the video subsystem, which makes its own adjustments to the performance of the entire system as a whole. The result of memory latency was surprising, although if you look closely at the graph, it becomes clear why the indicators are exactly what they are. Decreasing with increasing frequency and decreasing timings from the DDR2-533 4-4-4-12 mode, the latency has a "failure" on DDR2-667 3-4-3-9, and the latter mode practically does not differ from the previous one except for the frequency. And thanks to such low latencies, DDR2-667 easily overtakes DDR2-800, which has higher values, but the bandwidth of DDR2-800 still allows it to take the lead in real applications.

And in conclusion, I would like to say that despite a small percentage increase in performance (~ 0.5-8.5), which is obtained from a decrease in time delays, the effect is still present. And even when switching from DDR2-533 to DDR2-800, we get an average increase of 3-4%, and in WinRAR more than 20%. So such "tuning" has its advantages and allows you to slightly increase system performance even without serious overclocking.

Test results

Testing was carried out at timings from 5-5-5-15 to 9-9-9-24, and the frequency of RAM varied from 800 to 2000 MHz DDR. Of course, it was not possible to obtain results in all possible combinations from this range, nevertheless, the resulting set of values, in our opinion, is very indicative and corresponds to almost any possible real configurations. All tests were performed using the Super Talent P55 Memory Kit. As it turned out, these modules are capable of operating not only at 2000 MHz DDR, but also at 1600 MHz DDR at very low timings - 6-7-6-18. By the way, such timings were suggested to us by the first set - Super Talent X58. It is possible that both sets of modules use the same memory chips, and differ only in heatsinks and SPD profiles. On the graphs and in the tables of results, this mode of operation is marked as DDR3-1600 @ 6-6-6-18, so that the "slenderness" of the data presentation is not lost. In the graphs below, each line corresponds to the tests at the same bclk frequency and the same timings. Since the results are quite dense so as not to clutter the graphs, the numerical values ​​will be shown in the table below the graph. First, let's test in the Everest Ultimate synthetic package.

The RAM reading test shows that there is a performance gain from both increasing the memory frequency and decreasing its timings. Nevertheless, even for a specialized synthetic test, the increase is not very large, and with this type of graph, some points simply merge. In order to avoid this, if possible, we will change the scale of the vertical axis of the graph in order to display the entire range of the obtained values ​​as much as possible, as shown in the graph below.

Everest v5.30.1900, Memory Read, MB/s
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		15115	14908	14336	14098
	1333		14216	13693	13768	13027
	1066	13183	12737	12773	12060	12173
	800	11096	10830	10994	10700	10640
bclk=200 MHz	2000					18495
	1600		18425	17035	18003	17602
	1200		15478	15086	15467	15034

So, the test of reading from the memory of the Everest utility shows that with a 2-fold increase in the frequency of the RAM, its speed increases by a maximum of 40%, and the increase from a decrease in timings does not exceed 10%.

Everest v5.30.1900, Memory Write, MB/s
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		10870	10878	10866	10856
	1333		10859	10852	10854	10869
	1066	10852	10863	10851	10862	10870
	800	10873	10867	10841	10879	10864
bclk=200 MHz	2000					14929
	1600		14934	14936	14927	14908
	1200		14931	14920	14930	14932

Surprisingly, the Everest memory write test turned out to be completely indifferent to changing the frequency and timings of the RAM. But the result is clearly visible from the increase in the frequency of the cache memory of the third level of the processor by 50%, while the speed of the RAM increases by about 37%, which is quite good.

Everest v5.30.1900, Memory Copy, MB/s
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		15812	15280	15269	15237
	1333		15787	15535	15438	15438
	1066	16140	15809	14510	14344	14274
	800	13738	13061	13655	15124	12783
bclk=200 MHz	2000					20269
	1600		20793	19301	19942	19410
	1200		18775	20810	18087	19196

The in-memory copy test shows very inconsistent results. There is a noticeable increase in speed from an increase in the frequency of bclk, and in some cases a very noticeable effect of timings.

Everest v5.30.1900, Memory Latency, ns
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		45.4	46.7	46.9	48.5
	1333		48.3	48.7	50.8	53
	1066	51.1	51.4	53.9	56.3	58.6
	800	54.7	57.9	58.5	59.1	61.5
bclk=200 MHz	2000					38.8
	1600		39.7	41	41.2	42.9
	1200		42.5	44.6	46.4	48.8

The memory latency test shows generally expected results. However, the result in DDR3-2000 @ 9-9-9-24 mode is better than in DDR3-1600 @ 6-6-6-18 mode at bclk=200 MHz. And again, increasing the frequency of bclk leads to a significant improvement in the results.

Everest v5.30.1900, CPU Queen, scores
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		30025	30023	29992	29993
	1333		30021	29987	29992	30001
	1066	29981	30035	29982	30033	29975
	800	29985	29986	29983	29977	29996
bclk=200 MHz	2000					29992
	1600		29989	29985	30048	30000
	1200		30011	30035	30003	29993

As you can see, in this purely computational test, there is no influence of either the frequency or timings of the RAM. Actually, that's how it should have been. Looking ahead, let's say that the same picture was observed in the rest of the Everest CPU tests, with the exception of the Photo Worxx test, the results of which are shown below.

Everest v5.30.1900, PhotoWorxx, KB/s
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		38029	37750	37733	37708
	1333		36487	36328	36173	35905
	1066	33584	33398	33146	32880	32481
	800	27993	28019	27705	27507	27093
bclk=200 MHz	2000					41876
	1600		40476	40329	40212	39974
	1200		37055	36831	36658	36152

There is a clear dependence of the results on the frequency of the RAM, but they practically do not depend on the timings. We also note that, all other things being equal, there is an increase in results with an increase in the speed of the cache memory of the third level of the processor. Now let's see how the frequency of RAM and its timings affect performance in real applications. First, we present the test results in the built-in WinRar test.

WinRar 3.8 benchmark, multi-threading, Kb/s
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		3175	3120	3060	2997
	1333		3067	3023	2914	2845
	1066	2921	2890	2800	2701	2614
	800	2739	2620	2562	2455	2382
bclk=200 MHz	2000					3350
	1600		3414	3353	3305	3206
	1200		3227	3140	3020	2928

The picture looks just exemplary, the influence of both frequency and timings is clearly visible. But at the same time, doubling the frequency of RAM leads to a maximum of 25% increase in performance. Reducing the timings allows you to achieve a good performance boost in this test. However, in order to achieve the same results as with increasing the frequency of the RAM by one step, it is necessary to lower the timings by two steps at once. We also note that increasing the RAM frequency from 1333 to 1600 MHz gives a smaller performance boost in the test than when going from 1066 to 1333 MHz DDR.

WinRar 3.8 benchmark, single-threading, Kb/s
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		1178	1165	1144	1115
	1333		1136	1117	1078	1043
	1066	1094	1073	1032	988	954
	800	1022	972	948	925	885
bclk=200 MHz	2000					1294
1600		1287	1263	1244	1206
1200		1215	1170	1126	1085

In the single-threaded WinRar test, the picture generally repeats the previous one, although the growth of the results is more "linear". However, when increasing the memory frequency by one step, to achieve results, you still need to lower the timings by two steps or more. Now let's see how changing the frequency of RAM and its timings affects the test results in the Crysis game. First, let's set the "weakest" graphics mode - Low Details.

Crysis, 1280x1024, Low Details, No AA/AF, FPS
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		184.5	183.4	182.5	181.4
	1333		181.2	181.1	179.6	178.1
	1066	179.6	178.0	174.9	172.1	169.4
	800	172.4	167.9	166.0	163.6	165.0
bclk=200 MHz	2000					199.4
	1600		197.9	195.9	195.9	193.3
	1200		194.3	191.3	188.5	184.9

As can be seen from the graphs, the impact of timings is most noticeable at low RAM frequencies - 800 and 1066 MHz DDR. With a RAM frequency of 1333 MHz DDR and higher, the influence of timings is minimal and is expressed only in a couple of FPS, which is a few percent. Increasing the frequency of the third level cache affects the results much more tangibly. However, if we consider the absolute values, then directly in the game it will be very difficult to feel this difference.

Crysis, 1280x1024, Medium Details, No AA/AF, FPS
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		96.6	97.4	97.6	94.6
	1333		95.5	95.8	93.3	92.8
	1066	95.7	94.0	92.5	90.1	89.6
	800	91.6	89.0	88.6	86.2	86.3
bclk=200 MHz	2000					102.9
	1600		104.5	103.6	103.0	101.6
	1200		100.2	100.0	98.7	97.7

When you enable medium graphics in Crysis, the frequency of the RAM has more of an impact than its timings. The results obtained at bclk=200 MHz, regardless of the frequency and memory timings, are still superior to those at bclk=133 MHz.

Crysis, 1280x1024, High Details, No AA/AF, FPS
timings	DDR	5-5-5-15	6-6-6-18	7-7-7-20	8-8-8-22	9-9-9-24
bclk=133 MHz	1600		76.8	76.5	76.7	74.9
	1333		75.1	75.4	75.4	73.4
	1066	75.1	75.4	71.9	72.0	71.0
	800	71.8	69.7	69.0	68.6	66.7
bclk=200 MHz	2000					81.7
	1600		80.4	80.3	80.4	79.4
	1200		80.5	79.1	77.4	77.1

In general, the picture is preserved. Note that, for example, at a frequency of bclk=133 MHz, a twofold increase in the frequency of RAM leads to an increase in the results by only 12%. At the same time, the influence of timings at bclk=133 MHz is somewhat more pronounced than at bclk=200 MHz.

800 55.9 55.8 55.6 55.0 54.3 bclk=200 MHz 2000 59.5 1600 59.8 59.3 59.5 59.0 1200 59.4 58.9 58.7 59.0

When switching to the most "heavy" mode, the picture does not fundamentally change. Ceteris paribus, a 1.5-fold difference in the frequency of bclk leads to only a 5% increase in results. The impact of timings is within 1-1.5 FPS, and changing the frequency of RAM is only slightly more efficient. In general, the results are quite dense. Agree that it is very difficult to feel the difference between 55 and 59 FPS in the game. Note that the obtained values ​​of the minimum FPS almost completely coincided with the overall picture of the results for the average FPS, of course, at a slightly lower level.

⇡ Choosing the optimal RAM

Now let's look at the next point - how the performance of RAM compares to its price, and which ratio is the most optimal. As a measure of RAM performance, we took the results of testing in the built-in WinRar test using multithreading. Average prices at the time of writing were taken according to Yandex.Market data for single 1 GB DDR3 memory modules. Then, for each type of module, the performance indicator was divided by the price, that is, than less price and the higher the module performance, the better. The result is the following table.

DDR3	CAS Latency	WinRar benchmark, MB/s	Price, rub	Performance/price
1066	7	2800	1000	2.80
1333	7	3023	1435	2.11
1333	9	2845	900	3.16
1600	7	3120	1650	1.89
1600	8	3060	1430	2.14
1600	9	2997	1565	1.92
2000	9	3350	1700	1.97

For clarity, the diagram below shows the Performance/Price values.

Surprisingly, DDR3 memory running at 1333 MHz with 9-9-9-24 timings turned out to be the most optimal purchase in terms of performance / price. DDR3-1066 memory with 7-7-7-20 timings looks a little worse, while modules of other types demonstrate noticeably smaller (about 1.5 times relative to the leader), but rather similar results in this indicator. Of course, with regard to prices for memory modules, they can vary greatly in each specific case, and over time, the market situation as a whole may change somewhat. However, if necessary, it will not be difficult to recalculate the "Performance/Price" column.

⇡ Conclusions

As testing showed, in those applications where the increase in results from changing the frequency and timings of RAM was most pronounced, the increase in memory frequency had the greatest effect, and lowering the timings led to a noticeable increase in results much less often. At the same time, to achieve the same level of performance as with increasing the memory frequency by one step, as a rule, it was required to reduce the timings by two steps. As for the choice of RAM for Intel platforms LGA 1156, then enthusiasts and extreme people, of course, will stop their eyes on the most productive products. At the same time, DDR3-1333 memory working with 9-9-9-24 timings will be quite enough for typical tasks of an ordinary user. Since this type of memory is widely represented on the market and is very affordable, you can save a lot on the cost of RAM, while losing almost nothing in performance. The Super Talent X58 memory kit reviewed today made a somewhat ambiguous impression, and the Super Talent P55 kit was very pleased with both the stability of work and the ability to overclock and change timings. Unfortunately, at the moment there is no information on the retail price of these memory kits, so it is difficult to give any specific recommendations. In general, the memory is very interesting, and one of the features worth noting is the ability to work at relatively low timings and the fact that increasing the voltage on the modules practically does not affect the overclocking results.

Today we will talk about the most accurate definition of timings and sub-timings. Most articles on the net have errors and inaccuracies, and very worthy materials do not always cover all timings. We will try to fill this gap and give as complete a description of one or another time delay as possible.

The memory structure resembles a table, where a row is selected first, and then a column. This table is divided into banks, for memory with a density less than 64Mbit (SDRAM) there are 2 pieces, above - 4 (standard). The specification for DDR2 SDRAM memory with 1Gbit density chips already provides for 8 banks. It takes more time to open a line in the used bank than in another (because the used line must be closed first). Obviously, it is better to open a new line in a new bank (the principle of line alternation is based on this).

Usually on the memory (or in the specification for it) there is an inscription like 3-4-4-8 or 5-5-5-15. This is an abbreviated record (the so-called timing scheme) of the main memory timings. What are timings? Obviously, no device can run at infinite speed. This means that any operation takes some time to complete. Timings is a delay that sets the time required to execute a command, that is, the time from sending a command to its execution. And each number indicates exactly how long it takes.

Now let's take each one in turn. The timing scheme includes CL-Trcd-Trp-Tras delays, respectively. To work with memory, you must first select the chip with which we will work. This is done with the CS# (Chip Select) command. Then the bank and line are selected. Before you can work with any line, you must activate it. This is done by the RAS# row selection command (it is activated when a row is selected). Then (during a linear read operation), you need to select a column with the CAS# command (the same command initiates a read). Then read the data and close the line by pre-charging the bank.

The timings are arranged in order in the simplest query (for ease of understanding). Timings come first, then sub-timings.

Trcd, RAS to CAS delay- the time required to activate the row of the bank, or the minimum time between the signal to select the row (RAS#) and the signal to select the column (CAS#).

CL, Cas Latency- the minimum time between the issuance of a read command (CAS) and the start of data transfer (read latency).

Tras, Active to Precharge- the minimum time of row activity, that is, the minimum time between the activation of the row (its opening) and the command for pre-charge (the beginning of the closing of the row). The row cannot be closed before this time.

Trp, Row Precharge- the time required to pre-charge the bank (precharge). In other words, the minimum row closing time after which a new bank row can be activated.

CR, Command Rate 1/2T- The time required for the controller to decode commands and addresses. Otherwise, the minimum time between two commands. With a value of 1T, the command is recognized for 1 cycle, with 2T - 2 cycles, 3T - 3 cycles (so far only on the RD600).

These are all basic timings. The rest of the timings have a smaller impact on performance, and therefore they are called sub-timings.

Trc, Row Cycle Time, Activate to Activate/Refresh Time, Active to Active/Auto Refresh Time - minimum time between activation of rows of the same bank. It is a combination of Tras+Trp timings - the minimum time the line is active and the time it closes (after which you can open a new one).

Trfc, Row Refresh Cycle Time, Auto Refresh Row Cycle Time, Refresh to Activate/Refresh Command Period - minimum time between a command to update a row and an activation command or another update command.

Trd, ACTIVE bank A to ACTIVE bank B command, RAS to RAS Delay, Row Active to Row Active - minimum time between activation of rows of different banks. Architecturally, you can open a row in another bank immediately after opening a row in the first bank. The limitation is purely electrical - it takes a lot of energy to activate, and therefore, with frequent activation of the strings, the electrical load on the circuit is very high. To reduce it, this delay was introduced. Used to implement the memory access interleaving function.

Tccd, CAS to CAS Delay - minimum time between two CAS# commands.

Twr, Write Recovery, Write to Precharge - the minimum time between the end of a write operation and the command to precharge a row for one bank.

Twtr, Trd_wr, Write To Read - the minimum time between the end of writing and the issuance of a read command (CAS#) in one rank.

RTW, Read To Write, (Same) Rank Read To Write - the minimum time between the end of a read operation and the issuance of a write command, in one rank.

Same Rank Write To Write Delayed- the minimum time between two commands to record in the same rank.

Different Rank Write to Write Delay- the minimum time between two teams to record in different ranks.

Twr_rd, Different Ranks Write To READ Delayed - the minimum time between the end of writing and the issuance of a read command (CAS#) in different ranks.

Same Rank Read To Read Delayed- the minimum delay between two read commands in the same rank.

Trd_rd, Different Ranks Read To Read Delayed - minimum delay between two read commands in different ranks.

Trtp, Read to Precharge - the minimum interval between the issuance of a read command before the command to precharge.

Precharge to Precharge- minimum time between two pre-charge commands.

tpall_rp, Precharge All to Active Delay - delay between the Precharge All command and the line activation command.

Same Rank PALL to REF Delayed- sets the minimum time between Precharge All and Refresh in the same rank.

Different Rank REF to REF Delayed- sets the minimum delay between two commands to update (refresh) in different ranks.

Twcl, Write Latency - delay between the issuance of a write command and the DQS signal. Similar to CL, but for the record.

Tdal, quoted from JEDEC 79-2C, p.74: auto precharge write recovery + precharge time (Twr+Trp).

Trcd_rd/Trcd_wr, Activate to Read/Write, RAS to CAS Read/Write Delay, RAW Address to Column Address for Read/Write - combination of two timings - Trcd (RAS to CAS) and rd/wr command delay. It is the latter that explains the existence of different Trcd - for writing and reading (Nf2) and BIOS installation - Fast Ras to Cas.

Tck, Clock Cycle Time - period of one cycle. It is he who determines the frequency of memory. It is considered as follows: 1000/Tck=X Mhz (real frequency).

CS, Chip Select - the time required to execute the command given by the CS# signal to select the desired memory chip.

Tac, DQ output access time from CK - time from clock edge to data output by the module.

Address and Command Setup Time Before Clock- the time for which the transmission of command address settings will precede the rising edge of the clock.

Address and Command Hold Time After Clock- the time for which the address and command settings will be "locked" after the falling edge of the clock.

Data Input Setup Time Before Clock, Data Input Hold Time After Clock- same as above, but for data.

Tck max, SDRAM Device Maximum Cycle Time - maximum device cycle time.

Tdqsq max, DDR SDRAM Device DQS-DQ Skew for DQS and associated DQ signals - maximum shift between DQS strobe and associated data signals.

Tqhs, DDR SDRAM Device Read Data Hold Skew Factor - maximum "lock" shift of read data.

tch, tcl, CK high/low pulse width - the duration of the high/low level of the clock frequency CK.

Thp, CK half pulse width - the duration of the half cycle of the clock frequency CK.

Max Async Latency- maximum asynchronous delay time. The parameter controls the duration of the asynchronous delay, which depends on the time required for the signal to pass from the memory controller to the farthest memory module and back. The option exists in AMD processors (Athlon/Opteron).

DRAM Read Latch Delay- a delay that sets the time required for the "locking" (unambiguous recognition) of a particular device. Actual when the load (number of devices) on the memory controller increases.

Trepre, Read preamble - the time during which the memory controller delays the activation of data reception before reading, in order to avoid data corruption.

Trpst, Twpre, Twpst, Write preamble, read postamble, write postamble - the same for writing and after receiving data.

Read/Write Queue Bypass- specifies the number of times the earliest request in the queue can be bypassed by the memory controller before being executed.

Bypass Max- determines how many times the earliest entry in the DCQ can be bypassed before the arbitrator's choice is annulled. When set to 0, the choice of arbitrator is always taken into account.

SDRAM MA Wait State, Read Wait State - setting 0-2-cycle advancing of address information before the CS# signal is given.

Turn-Around Insertion- delay between cycles. Adds a one-tick delay between two consecutive read/write operations.

DRAM R/W Leadoff Timing, rd/wr command delay - delay before executing a read/write command. Usually 8/7 or 7/5 bars, respectively. The time from issuing a command to activating the bank.

Speculative leadoff, SDRAM Speculative Read - Usually, the memory receives the address first, then the read command. Since it takes a relatively long time to decode an address, it is possible to apply preemptive start by issuing an address and a command in succession without delay, which improves bus utilization and reduces downtime.

Twtr Same Bank, Write to Read Turnaround Time for Same Bank - the time between the termination of the write operation and the issuance of a read command in the same bank.

Tfaw, Four Active Windows - minimum time for four windows (active rows) to be active. It is used in eight-bank devices.

Strobe Latency. Delay when sending a strobe pulse (selector pulse).

Memory Refresh Rate. Memory refresh rate.

We hope that the information presented by us will help you understand the designation of memory timings, how important they are and what parameters they are responsible for.